Signal converter circuits having constant input and output impedances



May 28, 1968 1.. w. PRIDDY 3,386,053

SIGNAL CONVERTER CIRCUITS HAVING CONSTANT INPUT AND OUTPUT IMPEDANCESFiled April 26, 1965 SOURCE AC OR 0c 2 48 b VSQUARING AMP.

I I2? |29 SOURCE 77 AC 0 DC 93 lol n9 180 REE I09 23 INVENTOR.

LLOYD W. PRIDDY ATTORNEY 3.3%,053 SIGNAL CONVERTER CHRCUHTS HAVHNG CON-STANT INPUT AND OUTPUT IMPEDANCES Lloyd W. Priddy, Mahtomedi, Minn,assignor to Honeywell lino, Minneapolis, Minn a corporation of DelawareFiled Apr. 26, 1965, der. No. 450,930 11 Claims. (Cl. 332-431) AESTRAETOF THE DISELOSURE Signal converting circuitry formodulating-demodulating input signals while maintaining constant inputand outut impedances.

This invention pertains generally to transistor circuitry and moreparticularly to improved modulator and demodulator circuit design.

'Prior art modulators and demodulators have suffered from a number ofdeficiencies. One of the deficiencies being that an .ofiset or erroroutput voltage will often appear during the time period when thedemodulator is supposed to be switched to an OFF condition and no outputsignal is supposed to be provided. The apparatus receiving this signalwill of course integrate it into the results of the signal receivedduring the time the switch is ON and thus provide erroneous information.A second source of trouble in prior art demodulators lies in the factthat the impedence looking back from the output terminal is quite oftenvaried depending upon whether the switches in the half-wave version arein an OFF or an ON condition. The same problem of variation in impedanceoccurs looking into the demodulator and therefore there is a variationin drain current from the source of signal whether it be a DC sourcebeing modulated or an AC source being demodulated.

The two embodiments of this invention which are illustrated each solveone or more or the above mentioned problems. It is therefore an objectof this invention to provide improved modulating and demodulatingapparatus.

Further objects and advantages of the present invention may beascertained from a reading of the specification and claims inconjunction with the drawing in which:

FIGURE 1 is a schematic diagram of a simplified version of themodulator-demodulator apparatus; and

FIGURE 2 is a schematic diagram of a somewhat more advanced version ofthe modulating-demodulating apparatus for higher accuracy applications.

In FIGURE 1 a signal source it) supplies an output signal to a sourceelectrode 12 of an N-channel field effect transistor (PET) 14. Avariable potentiometer 16 has a resistance element 18 and a wiper 20.The wiper 2a is connected to an output terminal 22 while the resistanceelement 18 is connected between a drain electrode 24 of the FET 14 and asource 26 of a P-c-hannel FET 28 having a gate 30 and a drain 32. Aresistor 34 is connected between source 12 and a junction point 36 whichis further connected to a gate 38 of BET 14. A capacitor 4d and a diode42 are connected in parallel between junction point 36 and junctionpoint 44 which serve as an output terminal of a squaring amplifiergenerally designated as 46 and which has an input 48. A resistor 58 isconnected between drain 32 of PET 28 and a junction point designated as52. The drain 32 is further connected to ground or reference potential54. A diode 56 is connected in parallel with a capacitor 53 between thejunction point 44 and junction point 52. The diode 42 is connected suchthat its direction of easy current flow is toward junction point3,386,053 Patented May 28, 1968 44 while the diode 56 is connected sothat the direction of easy current flow is away from junction point 44.

FIGURE 2 is very similar to FIGURE 1 with the exception that all theFETs are of the N-type channel ma terial and there is compensation toallow the input impedence to remain constant throughout the use of theapparatus. However, the various portions will be given new numbers eventhough they are basically the same as in FIGURE 1. A signal source hasan output connected to a junction point 77 which is further connected toa source 79 of a PET generally designated as 81 further having a drain83 and a gate 85. A resistor 87 is connected between junction point 77and gate 85. A diode 8-9 is conneoted between .gate and a 0 referenceswitching signal input terminal 91 such that the direction of easycurrent flow is toward terminal 91. A resistor 93 is connected betweenjunction'point 77 and a source 95 of a PET generally designated as 97and having a gate 99 and a drain 101. A resistor 103 is connectedbetween drain 101 which is further connected to a source of positivevoltage 105 and gate 99. A diode 107 is connected between gate 99 and asource of 11' phase or 180 reference switching signal voltage 1G9. Adiode 111 is connected between terminal 109 and a gate 113 of a PETgenerally designated 115 and having a source 117 and a drain 1 19.Diodes 107 and M1 are both connected so that the direction of easycurrent how is toward terminal 109. A resistor .121 is connected betweengate 113 and ground or reference potential 123. Ground 123 is furtherconnected to drain 119 of PET lllii. A variable resistance orpotentiometer generally designated at 125 has a resistance element 127connected between drain and source 117 of FETs 8-1 and T15 respectively.Potentiometer 125 also has a wiper 129 connected to an output terminal131. As will be realized the 0 and reference voltage could easily besupplied from a differential squaring amplifier which with a singleinput signal would provide two output signals 180 out of phase.

While in the above description of the contents of this circuit thevarious FETs have been described as transistors, it will be realizedthat any other semi-conductor switches may be used to practice theinvention along with other types of electronic switches and therefore itis within the scope of the invention to use terminology for these EETssuch as valve means, gate means, variable impedance means, switch means,and semiconductor switching elements. Further, the resistive elementshave been designated as resistors for convenience and it is conceivablethat other types of impedence elements may be used in some situations.As will be noted, the two FE'IS in FIGURE 1 could be of the same channeltype by merely applying opposite phase signals to the diodes 42 and 56and further connecting them to have their direction of easy current flowthe same way. Likewise, the apparatus of lF-SEGUR E 2 could use a singleinput signal by merely making the PET 8'1 the opposite conductivity typeof PETS 97 and i 15 and changing the diode 89 accordingly.

OPERATION Before attempting to describe the circuitry of FIGURE 1 someof the fundamentals of FETs when used as switches should be stated. AnPET is in an open condition when no signal is applied thereto. In otherwords the drain and the source have a low impedance connectiontherebetween. When a signal is applied to the gate, the impedance isincreased between the source and the drain until it becomes a maximum.The circuitry of FIGURE 1 will work at least marginally even if theresistors 34 and 5t) and the capacitors 40 and 58 are removed. However,with the PETS connected in this manner (the named resistors andcapacitors removed) the FETs will amplify noise signals and otherextraneous signals when the diode 42 is back biased prior to the timethe internal capacitance of PET 14 is discharged. Since there is nodischarge path, the PET will have to discharge through the leakage pathof diode 42. This will take a considerable period of time and there willbe a large amount of noise in the output. The addition of resistor 34would prevent the gate 38 from floating and adding noise signals whendiode 42 is back biased but will tend to load down the source 1% if 34is a low impedance. If resistor 34 is a high impedance, the capacitanceinternal to PET 14 will still take a long time to discharge even thoughthis time is quite short as compared to removing the resistor entirely.If source can be loaded and not produce detrimental effects, theresistor 34 can be made quite small to allow a quick discharge of theinternal capacitance of PET 14 and everything will be satisfactory.However, if source 10 can not be loaded, it may be necessary to includethe capacitor 4%. Capacitor 40 will provide an extra kick on thepositive half cycle input from squaring amplifier 46 to supply currentof a positive value to charge the internal capacitance of PET 14 andtherefore allow PET 14 to turn to an ON condition and pass currenttherethrough. When the output from the squaring amplifier suddenly goesnegative, the capacitor 40 will lower the potential of gate 38 andabsorb current from the internal capacitance of PET 14 so as todischarge this internal capacitance more quickly. As will be noted, aresistor which functions in a manner similar to that of resistor 34 isused with all the rest of the PETs in this invention. The capacitorsimilar to that of capacitor 40 is used only in FIGURE 1 although theycould be used in FIGURE 2 if desired in some applications. However,FIGURE 2 has an additional function which eliminates part of therequirement of a large impedance for resistor 34 and thus in someapplications can do away with the requirement for a capacitor similar tothat of capacitor 40.

In the operation of FIGURE 1 as a demodulator, an alternating signal issupplied from source 10 and a switching signal is supplied from squaringamplifier 46. The switching signal will turn PET 14 ON at the sameinstant that PET 28 is turned OFF. Thus when the signal at junctionpoint 44 is positive, PET 14 will be ON and pass a signal from source 10to the output 22 and when the signal is negative at 44 the output 22will be connected directly to ground 54 through PET 28. A resistor couldbe used between drain 24 and ground 54 to provide a somewhat stableimpedance looking back into the demodulator but this would have to be animpedance such that there would be no appreciable change in theimpedance seen by the load. This would mean that the resistance betweendrain 24 and ground would be of a low value as compared with the outputimpedance of source 10. If this were of a low value, the load currentfrom source 10 would be very large when PET 14 is in an ON condition andthere would be an offset voltage at 22 due to leakage currents throughPET 14 when it is in the OPP condition. The circuit as shown eliminatesor substantially reduces this change in impedance looking into thedemodulator from output 22 since the wiper of potentiometer 16 isadjusted so that the impedance looking into output terminal 22 is thesame whether PET 14 or PET 23 is in an ON condition. Thus the source ofdemodulated signals presents a constant output impedance and the load isnot affected. Further there is no appreciable load on source 10 when PET14 is ON since the impedance of PET 28 is very high at this time due toits OPP condition.

When this circuit of FIGURE 1 is used as a modulator, the circuitconditions are exactly the same except that the input is either a slowlyvarying direct or alternating voltage or else a high frequency carrieras compared to the frequency of the switching or reference voltageapplied to terminals 48. In any event the operation of the circuit isexactly the same.

It may thus be observed that this is a very simple circuit for universaluse as a demodulator or modulator without any changes whatsoever.

FIGURE 2 provides an improved version for high accuracy applicationswhere the circuitry of FIGURE 1 is such that too much of a load isplaced on source 75. It is also used where the source can stand a largeload current but where it can not tolerate alterations in load current,in other words, where source 75 should .not be subjected to loadimpedance variations. The operation of PETs 81 and 115 are substantiallythe same as the operation of corresponding PETS 14 and 28 in FIG- URE 1with the exception that in FIGURE 2 the PETs are on the same N-channeltype and therefore must have opposite polarity switching signals appliedthereto. When a negative signal is applied to PET 81, there will be adrain current flowing from source 75 through resistor 8'7, diode 3% andout terminal 91 to the source of the switching signal. When the input toterminal 91 is positive, diode 89 is back biased and this source ofcurrent fiow is no longer in existence. However, at this time there willbe a current flow from source 75 through PET 81 to the load attached toterminal 131. One way to minimize the current flow variations fromsource 75 would be to insert a signal into the circuit during the timesthat PET 81 is OPP which is equal to the current flow through resistor87. This can be accomplished by connecting PET 97 to a source ofpositive potential and switching it to an ON condition when PET 81 isswitched OPP. The resistor 93 can then be adjusted or selected so thatthere is a current flow from terminal through PET 97, resistor 93,resistor 87, diode 89, and to the source of reference signal connectedto terminal 91. However, there would still be a variation in loadcurrent from source 75 which would be the difference between the currentflowing to the load when PET 81 is ON and the absence of current whenPET 81 is OPP. To correct this, the value of resistance 93 incombination with the ON impedance of PET 97 can be adjusted such thatthis current plus the current from source 75 through the load when PET81 is ON is the same as the current which would flow through resistor 87when PET 81 is in the OPP condition. Thus, the current flow from source75' would be the same whether PET 81 were in the OFF or ON condition andthere is no variation in the load current from source 75. As previouslyexplained in connection with FIGURE 1, source 75 can provide eitheralternating voltage for demodulation or direct voltage or current formodulating purposes. Also, if there is a variation in frequency betweensource 75 and switching signals applied to terminals 91 and 109, analternating signal can be modulated in a manner similar to that ofmodulating a carrier frequency in transmission or communicationapplications.

While two embodiments have been described, it will be realized by thoseskilled in the art that many individual variations of the basic circuitshown can be designed and I wish to be limited only by the appendedclaims wherein I claim:

1. Signal converting means wherein the input and output impedancesremain substantially constant comprising, in combination:

signal input means for supplying input signals;

switching input means for supplying switching signals;

output means for supplying output signals indicative of said input andswitching signals;

reference potential means;

variable impedance means connected to said output means and having firstand second inputs whereby the impedance between said output means andthe first input means of said variable means is increased as theimpedance between said output means and the second input means of saidvariable impedance means is decreased;

first FET switching means connected between said sigmeans is in saidfirst condition which is substantialnal input means and the first inputmeans of said ly equal to the differential current flow if said thirdvariable impedance means for providing first and switching means wereremoved to stabilize the apsecond conductivity conditions thcrebetweenand conparent impedance at said input means. nected to said switchinginput means to receive the 3. Signal dcmodulating means havingsubstantially conswitching signals therefrom, said first FET switchstantinput and output impedance comprising, in coming means changing betweenconductivity states in bination: response to corresponding changes ofthe switching input means for supplying an input signal; signalsreceived; output means for providing a converted output signal; secondFET switching means connected between said periodically switched firstgate means connected bereference potential means and the second inputmeans of said variable impedance means for providing first and secondconductivity conditions therebetween and connected to said switchinginput means to receive a signal therefrom, said first FET switchingmeans changing between conductivity states in response to correspondingchanges of a switching signal received from said switching input means,the conductivity states of said second FET switching means beingopposite the conductivity states of said first PET switching means;

tween said input means and said output means for alternately limitingand permitting signal flow therebetween;

means for supplying current to said input means only when said gatemeans is limiting signal flow to reduce variations in effective input:impedance connected to said input means; and

second gate means connecting an impedance to said output means when saidfirst gate means is limiting signal flow therethrough to reducevariations in effective output impedance at said output means.

current supplying means; 4-. Switching circuitry including signal inputmeans third FET switching means connected between said Switching inputmeans, reference Potential means a signal input mgans a d aid currentsupplying mgans output Il'lfifil'lS wherein it is desired that llhfioutput imand connected to aid wit hi in t means f 13- pedance be keptsubstantially constant comprising, in comceiving switching signalstherefrom and changing bmatloni conductivity states in response thereto,said third Variable impedance means Connected to Said Output FETswitching means supplying a current to said input means when said firstPET switching means is means of the switching circuitry and having firstand second inputs whereby the impedance between said in said firstcondition which is substantially equal to Output means and the firstinput 11163118 0f aid varithe difference between the current flow fromsaid able means is increased as the impedance between input means whensaid first PET switching means is Said Output means and the Second putmeans f in the first and second conductivity conditions and Saidvariable impedance means is decreased; h id hi d P i hi mgans i removedto first PET switching means connected between said sigstabilize theapparent impedance at said input means. ml input means and the firstinput means f Said 2, Si l mi means omprising wmbinavariable impedancemeans for providing first and tion: second conductivity conditionstherebetween and coninput i l Supp1ying means; nected to said switchinginput means to receive a switching signal supplying means; signaltherefrom, said first PET switching means Output means f suplying outputsignals; changing between conductivity states in response to referencepotential means; corresponding changes of a switching signal receivedvariable impedance means connected to said output from531dswttchlrlgirlputmeflns;and

means and having fi and Second inputs whereby second PET sw tch meansconnected between said refthe impedance betwen said output means and theerencft potrltlal means and the Second input means fi t input means andsecond input means f i of said variable impedance means for providingfirst variable means varies inversely; and second conductivityconditions therebetwcen and first switching means connected between saidinput sigcPnnected to Sald Switching p means t r ive 3 1 Suplflyjngmeans and the fi t input means of signal therefrom, said first FETswitching means i variable impedance means for providing first changingbetween conductivity states in response to and second conductivityconditions therebetween and cofrespondlng f Q the Switching Signalconnected to said switching signal supplying means from 531d Switchinginput mfiarls, the C011- to receive switching signals therefrom, saidfirst duFtlvlty states of said f r FET Switch a s switching meanschanging between conductivity states @mg PP F the conductlvlty States Ofaid fi st in response to corresponding changes of the switch- FETswltchufg means to P OVlde P to id refi i l received; erence potentialmeans at all times.

5. Switching circuitry including signal input means, switching inputmeans, reference potential means and output means comprising, incombination:

variable impedance means connected to said output second switching meansconnected between said reference potential means and the second inputmeans of said variable impedance means for providing first and secondconductivity conditions therebetween and means of the switchingcircuitry and having first and connected to said switching signalsupplying means 50 to receive a signal therefrom, said first switchingSecond Inputs whereby the impedance between Said means changing betweenconductivity states in re- Output P and firstarld Sewnd i put means ofsponse to corresponding changes of a switching signal sald Y f means 13Varled r y; received from said switching signal supplying means, tSwltchmg means Connected between Said Signal thg conductivity states fSaid Second Switching 65 nput means and the first input means of saidvariable means being opposite the conductivity states of said Impedancef t for Providing st and S cond confir t switching means; ductivityconditions therebetween and connected to current supplying means; saidswitchlng input means to receive a signal therethird switching meansconnected between said input from, first SWItQhmg means changingbetWEfin i l l i means d i current supplying conductivity states inresponse to corresponding means and connected to said switching signalsup- Charlgfis of a Switching Signal received rom said plying means forreceiving switching signals there- Switching input means; and from andchanging conductivity states in response second switching meansconnected between said refthereto, said third switching means supplyinga curerence potential means and the second input means rent to saidinput means when said first switching of said variable impedance meansfor providing first and second conductivity conditions therebetween andconnected to said switching input means to receive a signal therefrom,said first switching means changing between conductivity states inresponse to corresponding changes of the switching signal received fromsaid switching input means, the conductivity states of said secondswitching means being opposite the conductivity states of said firstswitching means. 6. Apparatus of the class described comprising, incombination:

first means for supplying a first input signal; second means forsupplying a second input signal to be used as a switching signal; outputmeans for supplying an output signal which is a function of said firstand second signals; potentiometer means having a wiper connected to saidoutput means; reference potential means; first and second field effecttransistor means each connected to said potentiometer means whereby saidfirst and second field effect transistor means and said potentiometermeans are connected in series and whereby said first and secondtransistor means are connected to said first means and said referencepotential means respectively; and third means connecting said secondmeans to said first and second field effect transistor means forapplying said second input signal thereto, said first and secondtransistor means being in opposite conductivity conditions at a giventime. 7. Apparatus of the class described comprising, in combination:

first means for supplying a first input signal; second means forsupplying a second input signal to be used as a switching signal; outputmeans for obtaining an output signal which is a function of said firstand second signals; variable impedance means having a tap connected tosaid output means; reference potential means; first and second fieldeffect transistor means each connected to said impedance means wherebysaid field effect transistor means and said impedance means areconnected in series and at opposite ends of said potentiometer meansbetween said first means and said reference potential means; and thirdmeans connecting said second means to said first and second field effecttransistor means for applying said second input signal thereto, saidfirst and second transistor means being in opposite conductivityconditions at a given time. 8. Apparatus of the class describedcomprising, in combination:

first means for supplying a first input signal; second means forsupplying a switching signal; output means for supplying an outputsignal which is a function of said first and second signals; impedancemeans having a tap connected to said output means; reference potentialmeans; first and second valve means each connected to said impedancemeans whereby said valve means and said impedance means are connected inseries and at pposite ends of said impedance means between said firstmeans and said reference potential means; and third means connectingsaid second means to said first and second valve means for applying saidsecond input signal thereto, said first and second valve means being inopposite conductivity conditions at a given time. 9. Improved half wavemodulator-demodulator apparatus having reference potential means, meansfor supplying a periodic switching signal, switch means con- 8 nectedbetween signal input and signal output means, said switch means havingcontrol means connected to said means for supplying a periodic switchingsignal, said switch means alternating between conductive andnon-conductive conditions in accordance with said periodic switchingsignal, wherein the impedance between said signal output means and saidreference potential means is subject to variation as said switch meansis periodically rendered conductive and non-conductive, wherein theimprovement comprises:

valve means having control means connected to said means for supplying aperiodic switching signal, said valve means alternating betweenconductive and nonconductive conditions in accordance with said periodicswitching signal and in phase opposition to the conductivity state ofsaid switch means; variable impedance means including end means andwiper means; means connecting said end means of said variable impedancemeans and said valve means in series between said signal output meansand said reference potential means; and improved signal output meansconnected to said Wiper means, wherein said wiper means is adjustable toproduce a substantially constant impedance with respect to saidreference potential means at said improved signal output means. 10.Half-wave modulator-demodulator apparatus comprising, in combination:

reference potential means; input signal means for connecting a sourcesupplying a signal to be modulated or demodulated, said source having acharacteristic series output impedance; output signal means; impedancemeans including first and second end means and wiper means, theimpedance between said wiper means and said first and second end meansvarying inversely upon adjustment of said wiper means between said firstand second end means; first switch means connected between said inputsignal means and said first end means of said impedance means, saidfirst switch means having control means; second switch means connectedbetween said second end means of said impedance means and said referencepotential means, said second switch means having control means; meansconnected to said control means for turning said first and second switchmeans OFF and ON alternately and periodically in phase opposition; andmeans connecting said wiper means to said output signal means forproviding a substantially constant output impedance with respect to saidreference potential means through adjustment of said wiper means. 11. Inhalf-wave modulator-demodulator apparatus wherein a series semiconductorswitch is used in combination with a biasing impedance whereby thecurrent drawn by the combination varies between two conductivity statesof the semiconductor switch so as to alter the effective inputimpedance, the method of stabilizing the apparent input impedancecomprising the step of adding a current to the apparatus input current,substantially equal to the difference in currents drawn by thecombination, during the conductivity state when the combination requiresthe greatest amplitude current flow.

References Cited UNITED STATES PATENTS 2,840,699 6/1958 Carpenter329-101 X 2,863,123 12/1958 Koch 332-31 3,160,767 12/1964 Tindall 3078853,139,846 6/1965 Millis et al. 329101 X 3,229,218 1/1966 Sickles et al.307-885 ALFRED L. BRODY, Primary Examiner.

